As a technique of fabricating a multilayer wiring board, a build-up method has been widely used. The build-up method typically includes the processes of forming an insulating layer, forming via holes in the insulating layer, and then forming a wiring layer while filling the via holes with a conductor (via). The processes are sequentially repeated on both sides of a core substrate serving as a base so that the layers are stacked on one another. In this structure, the wiring layers and the insulating layers can be formed to be thin because these layers are stacked by the build-up method. On the other hand, the core substrate requires a thickness large enough for the wiring board to have a certain rigidity. This hinders the reduction in thickness of the entire package.
For this reason, a structure without a core substrate (support base member) has been recently employed in order to achieve a further reduction in thickness of the wiring board (semiconductor package). The wiring board having such a structure is called a “coreless substrate” because the wiring board has no core. Although a detailed description of the method of fabricating the coreless substrate is omitted herein, the method basically includes the processes of forming pads on a temporary substrate serving as a support member, then forming build-up layers on the pads and the temporary substrate, and finally removing the temporary substrate (support member).
As one form of a semiconductor device using such a coreless substrate, there is a structure in which a semiconductor element is mounted on one surface of the substrate and external connection terminals are bonded to the other surface of the substrate. In the semiconductor device employing this structure, electrode pads of the semiconductor element (chip) are flip-chip connected via conductive bumps to pads (terminal portions) exposed from the one surface of the substrate. Namely, in the semiconductor device of this structure, the semiconductor chip having a coefficient of thermal expansion (CTE) largely different from a CTE of the substrate is mounted on the one surface of the substrate. Accordingly, distribution of the CTE is asymmetric in the up-and-down direction when the structure of the board is vertically viewed.
As another form of a semiconductor device designed to be thin by eventually removing the support member as in the case of the coreless substrate, there is a structure formed by burying a semiconductor element in a substrate, instead of surface-mounting the semiconductor element on the substrate. An example of the technique related to this structure is described in Japanese Laid-open Patent Publication No. 2006-222164 (hereinafter, referred to as Patent Document 1).
In a semiconductor device of the type in which a semiconductor element is surface-mounted on a wiring board, the element and the substrate are connected to each other through conductive bumps. This involves a problem in that it is not possible to make the pitch between the terminals of the element finer (to reduce the pitch) because the pitch depends upon the size of the bump. It is possible to reduce the pitch where the size of the bump is reduced. In this case, however, another problem occurs in that handling, or transfer of the solder balls onto the substrate, cannot be easily performed.
Moreover, the thickness of the entire semiconductor device is increased by the amount of the diameter of the bump. In addition, when the semiconductor element (chip or die) is mounted, a thickness large enough to provide a certain strength (not less than 100 μm in the state of the art) is needed due to the limitation on handling such as pick-up or die attachment. For this reason, a problem arises in that the thickness of the entire semiconductor device is further increased.
The semiconductor device of the type formed by burying the semiconductor element in the substrate, as described in Patent Document 1 above, uses no bump to connect the element and the substrate. Accordingly, the semiconductor device of this type does not have to deal with the aforementioned problem. However, the semiconductor devices of a structure in which the entire package is thinly formed (coreless substrate), inclusive of the semiconductor device described in Patent Document 1, have an up-and-down asymmetric structure. Specifically, the structure includes the insulating layers and the wiring layers stacked only on the electrode terminal side of the semiconductor element. Accordingly, the distribution of the coefficient of thermal expansion (CTE) is asymmetric in the up-and-down direction when the structure is vertically viewed. For this reason, there is a problem in that warp of the substrate easily occurs.
In addition, the semiconductor device of this structure poses a problem when it is applied to a so-called package-on-package (POP) structure or multi-chip package (MCP) structure. Specifically, no wiring or no external terminal is provided on a back surface side (i.e., the opposite side to the side on which electrode terminals are formed) of the element to be mounted on the substrate. For this reason, when a surface mount technology (SMT) component such as another package or a chip capacitor is mounted on the substrate, the layout of the terminals of the SMT component, or the mounting position thereof, is limited. As a result, the degree of freedom in the mounting is limited. In other words, the semiconductor device of this structure cannot be easily applied to a POP structure or the like without causing such an inconvenience.